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Implementing 1D Dirac Equation Simulation on Tang Nano 4K: An Experimental Plan

に公開
量子力学
FPGA
ディラック方程式
tech

1. Research Title

Implementation and Verification of Fixed-Point Time-Evolution Circuits for the 1D Dirac Equation using Tang Nano 4K

2. Background and Objectives

I have previously implemented a numerical simulation of the 1+1 dimensional Dirac equation using Processing, confirming the following phenomena:

  • Linear dispersion
  • Zitterbewegung (trembling motion)
  • Numerical instability dependent on dt

As the next step, I aim to:

Implement this abstract numerical model as a physical circuit on an FPGA
Verify the reproducibility of the structure under these constraints

In this research, using the resource-constrained Tang Nano 4K, I will implement the time evolution of the Dirac equation under the following conditions:

  • Sequential updates instead of parallel processing
  • Fixed-point arithmetic instead of floating-point
  • Minimal use of DSP resources

3. Research Hypotheses

No. Hypothesis
H1 Linear dispersion can be reproduced even with 16-bit fixed-point arithmetic
H2 The difference between m=0 and m≠0 is observable even in an FPGA implementation
H3 The norm is approximately conserved, but minor fluctuations occur due to fixed-point errors
H4 Settings for dt and dx strongly influence numerical stability

4. Experimental Model

4.1 Equation

i \partial_t \psi = (-i\sigma_x \partial_x + m\sigma_z)\psi

4.2 Discretization

  • Space: Central difference
  • Time: Forward Euler (initial stage)
  • Spinor components: 2-component

5. Implementation Environment

Item Specification
FPGA Tang Nano 4K (GW1NSR-4C)
Logic Scale Approx. 4K LUT
DSP Minimal use assumed
Numeric Format Q1.15 fixed-point
Lattice Points 128 or 256
Clock 27–50 MHz

6. Design Strategy

6.1 Parallel to Time-Division Multiplexing

Ideal Design Tang Nano Strategy
Parallel update of all lattice points Sequential updates
Numerous multipliers Single shared multiplier
Floating-point Fixed-point

6.2 Update Algorithm

Per-point update sequence:

  1. Read ψ[i-1], ψ[i], ψ[i+1]
  2. Calculate differences
  3. Calculate m-term
  4. Multiply by dt
  5. Write back

7. Circuit Overview

7.1 Block Diagram

Block Function
BRAM Store ψ lattice
Address Counter Lattice scanning
Difference Calculator (ψ[i+1]-ψ[i-1])
Fixed-point Multiplier Multiply by dt
Adder Update
UART/VGA Output Visualization

8. Experimental Parameters

Parameter Initial Value Range Purpose
m 0, 1 0–2 Confirm Zitterbewegung
dt 0.001 0.0005–0.02 Confirm stability
dx 0.05 Fixed Lattice stability
N 128 64–256 Resource evaluation

9. Evaluation Metrics

Evaluation Item Measurement Method
Norm Conservation Sequentially calculate Σ
Wave Packet Center Track position of maximum value
Zitterbewegung Amplitude Time variation of center position
Numerical Divergence Presence of amplitude explosion

10. Success Criteria

Level Criteria
Level 1 Confirm linear propagation at m=0
Level 2 Confirm oscillations at m≠0
Level 3 Norm fluctuation < 5%
Level 4 Reproduce dt-dependency

11. Potential Risks

Risk Mitigation Strategy
Fixed-point error accumulation Increase bit width
Numerical divergence Reduce dt
Insufficient LUTs Reduce lattice points
Insufficient clock speed Pipeline splitting

12. Expected Outcomes

  • Demonstration of structural reproduction under constraints
  • Understanding the relationship between numerical errors and physical structures
  • Confirmation of the feasibility of Dirac-type operations on FPGAs

13. Future Roadmap

  1. Implementation and experimentation
  2. Preparation of experimental report
  3. Analysis of correspondence between equations and circuits
  4. Reclaiming the meaning of the Dirac equation

14. Research Positioning (EDiE Perspective)

This research is not an attempt to physically realize quantum phenomena.

It is an attempt to expose the structure of the Dirac equation
within a constrained physical circuit.

The stricter the constraints, the clearer the structure becomes.

The Tang Nano 4K is the laboratory for this endeavor.

Next steps:

📌 Minimum Verilog template
📌 Fixed-point definition code
📌 BRAM configuration example

completed

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