PSFB DC/DC (ゼロから設計・自作・評価) | Phase-Shift Full Bridge DC/DC from scratch
DIY Phase-Shifted Full Bridge (PSFB) DC/DC Converter — Designed and Built from Scratch
- V_in: up to 48 V
- Power: up to ~110 W
- Iout: up to ~9 A
- Best efficiency: >80% (light load)
- High-load efficiency: ~65–71%
ゼロから設計・製作した自作PSFB DC/DCコンバータ（手巻きトランス含む）
- 入力電圧: 最大 48 V
- 出力電力: 約 110W
- 出力電流: 約 9 A
- 最高効率: 80%以上（軽負荷）
- 高負荷時効率: 約 65～71%
Contents 目次
-
Schematic & PCB Design（回路図・PCB設計）
Initial gate driver, MOSFET, pull-down, and power routing design
→ Lesson: Bootstrap capacitor charges through low side FET -
ESP32 Microcontroller PWM Setup（ESP32マイコンPWM設定）
MCPWM used to generate complementary half-bridge signals -
Deadtime Configuration Failure（デッドタイム設定の破綻）
Output overlap observed despite deadtime configuration
→ Lesson: Deadtime was not enforced symmetrically on both edges
https://zenn.dev/okadda1/articles/5be6b284c65bc8#firmware-source-code-on-a-generic-esp32-microcontroller-(partly-failed) -
Miller Effect on High-Side MOSFET（高サイドMOSFETのミラー効果）
dv/dt induced V_GS collapse and re-triggering
→ Lesson: Gate control is as critical as PWM timing -
Destructive Switching Event（破壊的スイッチング）
Parasitics and weak pull-down caused shoot-through and capacitor failure -
Why Deadtime Must Be Hardware-Enforced（デッドタイムがHW必須な理由）
Software timing could not safely handle fast switching transients -
ESP32 MCPWM Architectural Limitation（ESP32 MCPWMの限界）
MCPWM not designed for power-grade full-bridge deadtime enforcement
→ MCU selection must match power-stage physics
→ Power conversion needs purpose-built control hardware -
ASIC control
Design and test of a PCB for ASIC control, using Texas Instruments UCC3895DW
https://zenn.dev/okadda1/articles/5be6b284c65bc8#asic-control -
PSFB + transformer + passive rectification
Experimental transformer design, hand manufacture and verification tests -
Heating and efficiency
Estimating efficiency and power losses for each component.
https://zenn.dev/okadda1/articles/5be6b284c65bc8#heating-and-temperature-verification
→ Full bridge rectifier diodes cause significant power losses
→ Ringing due to Schottky diode capacitance and transformer leak inductance causes stress and additional losses at high current
→ Estimated losses from electrical measurements closely match thermal calculation based on IR temperature measurement
→ Copper losses on transformer and PCB traces become dominant at large output current
→ Transformer interleaved winding poorly constructed may be more efficient than a tidy but interleaved winding -
Control feedback loop and EMC
→ Twisted pair differential signal with dedicated AGND is key for long distance signal control. RC filters just provide limited mitigation
https://zenn.dev/okadda1/articles/5be6b284c65bc8#closed-control-%26-emc-measures｜-制御フィードバックとemi対策 -
Multi-pole transformer PSFB
作成中 Ongoing...
Overview 概要
🇬🇧 In this project, the target is to create an experimental board to implement a 3 phase BLDC motor inverter and a Phase Shift Full Bridge DC/DC converter that is asynchronous and full bridge on the secondary using a diode full bridge.
It has three half bridges, two of them used for the PSFB and three for the inverter.
The transformer and motor will be connected externally thorough the connectors on the right side of the schematic.
🇯🇵 このプロジェクトでは、3相BLDCモーターインバータと、二次側がダイオード全波整流の非同期フルブリッジ構成による位相シフトフルブリッジ（PSFB）DC/DCコンバータを実装するための実験用基板を作成することを目的としています。
本回路には3つのハーフブリッジがあり、そのうち2つはPSFB用、3つはインバータ用として使用します。
トランスおよびモーターは、回路図右側のコネクタを介して外部に接続されます。
PSFB MOSFET full bridge bring up
Initial schematics and PCB with EasyEDA CAD
電気図面(EasyEDA Pro)、以下
基板図面(EasyEDA Pro)、以下
3Dビュー(Easy EDA Pro)、以下
🇬🇧 As an initial prototype, I assembled part of the PCB (see photo below).
Instead of using PWM control, I first tried to turn on a single MOSFET
via a push button through the FAN7382 gate driver (this attempt was not successful).
🇯🇵 最初試作の基板を一部組立たら（以下写真）、まず、PWMではなく、押すボタンでFAN7382を介して一つのMOSFETをオンにしてみました（成功なし）。
🇬🇧 This approach helped me identify several wiring mistakes based on abnormal behaviors.
🇯🇵 そうすることで、いくつかの異常なふるまいで接続ミスを確認できました。
-
🇬🇧 When applying a 24 V input voltage, intermittent short circuits occurred. It was unclear whether the cause was a short circuit caused by components on the bottom side of the PCB, or shoot-through due to unintended MOSFET turn-on, since the gate-source pull-down resistors for the half-bridge MOSFETs were not populated.
As a precaution, I cut some legs and temporarily added pull-down resistors of a few hundred ohms. However, before adding the pull-down resistors, I checked Vgs with an oscilloscope and it remained at 0 V at all times.
🇯🇵２４Ｖ入力電圧を印加してみたら、断続的に短絡が発生しました。基板下側の部品が短絡が起こしていたのかハーフブリッジのMOSFETはGate-SourceのPull down抵抗値が配置されなく、誤動作オンによるShoot-throughという原因なのか判定できませんでしたが、念のため道具でカットや仮に数百Ω抵抗体追加で防ぐようにしました。但し、Pull down抵抗体を配置する前に、オシロスコープでVgsはずっと0Vでした。 -
🇬🇧 The voltage between PIN1 and PIN4 of the FAN7382 was 0 V. This was caused by the GND not being connected in the PCB design
🇯🇵FAN7382のPIN1とPIN4間電圧が0Vに達しました。基板を設計した際に、GNDが接続されていなかったです。 -
🇬🇧 The VS pin (PIN6) of the FAN7382 must be connected to the MOSFET source, but it was not connected on the PCB.
🇯🇵 FAN7382のVSピン6はMOSFETのSourceに接続する必要、基板では接続されていなかったです。 -
🇬🇧 Vcc is 23.6 V, and I measured 23.0 V on FAN7382 gate driver supply pins, besides intended to be roughly 10 V. Thanks to realizing this, I realized LM317 LDO voltage divider resistor should be between pin 2 and pin3, in the PCB is was between pin 1 and pin 3.
🇯🇵 Vccは23.6V、FAN7382の入力電源ピンで10V程度を目標していたのに、で23.0Vを測定しました。LM317 LDOの分圧抵抗体の接続ミスを確認できました。
以下の図面で表示されます。These issues are shown in the schematic below.
🇯🇵 ハイサイド MOSFET をオンにするため、FAN7382 の HIN に手動のプッシュボタンで HIGH 信号を入力してみましたが、何度試しても動作しませんでした。
調査した結果、FAN7382 の VS ピンが VCC に固定されている状態では、ブートストラップコンデンサが充電されない ことに気づきました。
実際の PWM 動作ではこの問題は発生しません。なぜなら、FAN7382 の LIN が先に HIGH になることで、VS ピンが COM（この場合は GND、0 V）に引き下げられ、ブートストラップコンデンサが正常に充電されるためです。
私は以前、ハイサイド MOSFET が 1 個だけの単純なハイサイド・バック DC/DC コンバータを扱った経験から、この現象が起きないものだと誤解していました。この点は、トポロジーの違いによるものでした。
⚠️ FAN7382 のデータシートではこの挙動が明確に説明されていないため、データシートのアプリケーション例を元に、
**ブートストラップコンデンサが充電されない状態（左）**と
**充電される状態（右）**を、図で分かりやすく説明しました。
🇬🇧 While trying to turn on the high side MOSFET by sending a HIGH signal to FAN7382 HIN with a manual push button, I failed repeatedly. I realized the boostrap capacitor of the FAN7382 does not charge due to VS being set to VCC. This does not happen in real PWM opeartion because when FAN7382 LIN goes to HIGH first, VS pin is set to COM (GND or 0 V in this case). I was under the wrong impression from my previous project of a single MOSFET, high side buck DC/DC, where this does not occur due to the topology.
⚠️Since the FAN7382 datasheet does not explicitly mention this, I created this diagram, based on the original datasheet application example, where I explained graphically when the bootstrap capacitor charges (right) and when not (left).
🇯🇵 次は、FAN7382のLINを断続的にON/OFFにすることで、Bootstrapコンデンサーを充電させ、LIN OFF
➡Deadtime遅延➡HIN ONという順番でHalfbridgeを動作する予定です。
⚠但し、FAN7382のLIN➡HIN➡LIN➡LIN変換の間に遅延（deadtime）をかけても、MOSFETのV＿GSの遅れや共振振る舞いが発生する見込みなでShoothroughは懸念点です。数ns時間の過電流だけで破壊されますので、VccとHigh side MOSFETの間に10Ωの抵抗体を配置します（Shootthroughが発生しても2.4 Aに抑制）。
🇬🇧 Next, the plan is to intermittently turn LIN of the FAN7382 ON and OFF in order to charge the bootstrap capacitor, and then drive the half-bridge in the following sequence: LIN OFF → dead time → HIN ON.
⚠️ However, even if a delay (dead time) is inserted during the LIN → HIN → LIN → LIN transitions, delays in the MOSFET V<sub>GS</sub> response and resonant behavior are expected. Therefore, shoot-through remains a concern. Since the MOSFETs can be destroyed by overcurrent lasting only a few nanoseconds, a 10 Ω resistor will be placed between V<sub>CC</sub> and the high-side MOSFET to limit the current to approximately 2.4 A in the event that shoot-through occurs.
Firmware source code on a generic ESP32 microcontroller (partly failed)
🇯🇵 Esspressif IDEで新規プロジェクトを作成、まず、HalfbridgeのPWM、位相や遅延をプログラミングしてみます。推奨作成方法は File > New > Espressif IDE Project > Create using template & ESP32C3 以下の画像の通り。
Buildをクリックした後、"Make" cannot be found on path: ...というエラーが出た場合、左側のProject MenuでParent folderをダブルクリックすることでPathは更新され、解決されることがあります。
🇬🇧 I create a new project in Espressif IDE, and first try programming the half-bridge PWM, including phase control and dead time. The recommended creation method is: File → New → Espressif IDE Project → Create using template → ESP32-C3, as shown in the image below.
If an error such as “Make cannot be found on path: …” appears after clicking Build, the issue may sometimes be resolved by double-clicking the Parent folder in the Project menu on the left, which refreshes the PATH.
🇬🇧 以下の通りに設定:
🇯🇵 Configure as below:
Finally, I programmed the ESP32 with the source code below (generated by OpenAI, not my own code) to give PWM duty 40% to one MOSFET and 60% to the other (exclusing deadtime).
#include <stdio.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_err.h"
#include "esp_log.h"
#include "driver/mcpwm_prelude.h"
static const char *TAG = "mcpwm_halfbridge";
// ====== USER SETTINGS ======
#define PWM_GPIO_A 17 // MCPWM output A -> gate driver input A
#define PWM_GPIO_B 18 // MCPWM output B -> gate driver input B
#define PWM_FREQUENCY_HZ 200000 // 200 kHz
#define PWM_DUTY 0.40f // 40% duty
// Deadtime in nanoseconds (tune for your MOSFET + driver)
#define DEADTIME_RISE_NS 300
#define DEADTIME_FALL_NS 300
// ==========================
void app_main(void)
{
ESP_LOGI(TAG, "Starting MCPWM half-bridge: f=%d Hz duty=%.2f deadtime=%dns/%dns",
PWM_FREQUENCY_HZ, PWM_DUTY, DEADTIME_RISE_NS, DEADTIME_FALL_NS);
// 1) Create a timer (defines PWM period)
mcpwm_timer_handle_t timer = NULL;
// Use 1 MHz resolution so 1 tick = 1 us (easy, robust).
// If you need finer duty/deadtime granularity at high freq, raise this (e.g., 10 MHz).
const uint32_t timer_res_hz = 1000000; // 1 MHz
// period_ticks = timer_res_hz / PWM_FREQUENCY_HZ
const uint32_t period_ticks = timer_res_hz / PWM_FREQUENCY_HZ;
mcpwm_timer_config_t timer_config = {
.group_id = 0,
.clk_src = MCPWM_TIMER_CLK_SRC_DEFAULT,
.resolution_hz = timer_res_hz,
.period_ticks = period_ticks,
.count_mode = MCPWM_TIMER_COUNT_MODE_UP,
};
ESP_ERROR_CHECK(mcpwm_new_timer(&timer_config, &timer));
// 2) Create operator and connect it to the timer
mcpwm_oper_handle_t oper = NULL;
mcpwm_operator_config_t oper_config = {
.group_id = 0,
};
ESP_ERROR_CHECK(mcpwm_new_operator(&oper_config, &oper));
ESP_ERROR_CHECK(mcpwm_operator_connect_timer(oper, timer));
// 3) Create comparators (one is enough since we want same duty on A/B)
mcpwm_cmpr_handle_t comparator = NULL;
mcpwm_comparator_config_t cmpr_config = {
.flags.update_cmp_on_tez = true, // update at timer equals zero (safe)
};
ESP_ERROR_CHECK(mcpwm_new_comparator(oper, &cmpr_config, &comparator));
// Set duty: compare value = duty * period_ticks
uint32_t compare_ticks = (uint32_t)(PWM_DUTY * (float)period_ticks);
if (compare_ticks >= period_ticks) compare_ticks = period_ticks - 1;
ESP_ERROR_CHECK(mcpwm_comparator_set_compare_value(comparator, compare_ticks));
// 4) Create two generators (A and B) on different GPIOs
mcpwm_gen_handle_t gen_a = NULL;
mcpwm_gen_handle_t gen_b = NULL;
mcpwm_generator_config_t gen_a_config = {
.gen_gpio_num = PWM_GPIO_A,
};
mcpwm_generator_config_t gen_b_config = {
.gen_gpio_num = PWM_GPIO_B,
};
ESP_ERROR_CHECK(mcpwm_new_generator(oper, &gen_a_config, &gen_a));
ESP_ERROR_CHECK(mcpwm_new_generator(oper, &gen_b_config, &gen_b));
// 5) Program waveform:
// For UP-count mode typical PWM:
// - set output HIGH at timer = 0 (TEZ)
// - set output LOW at compare match
//
// Generator A: active-high PWM
ESP_ERROR_CHECK(mcpwm_generator_set_action_on_timer_event(
gen_a,
MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_HIGH)
));
ESP_ERROR_CHECK(mcpwm_generator_set_action_on_compare_event(
gen_a,
MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, comparator, MCPWM_GEN_ACTION_LOW)
));
// Generator B: complementary (active-low version of A) BEFORE deadtime
// - set output LOW at timer = 0
// - set output HIGH at compare match
ESP_ERROR_CHECK(mcpwm_generator_set_action_on_timer_event(
gen_b,
MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_LOW)
));
ESP_ERROR_CHECK(mcpwm_generator_set_action_on_compare_event(
gen_b,
MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, comparator, MCPWM_GEN_ACTION_HIGH)
));
// 6) Insert deadtime between A and B (half-bridge safety)
// Make gen_b a delayed/complemented partner of gen_a.
//
// There are multiple deadtime modes; this one makes a proper non-overlap pair.
mcpwm_dead_time_config_t dt_config = {
.posedge_delay_ticks = (uint32_t)((uint64_t)DEADTIME_RISE_NS * timer_res_hz / 1000000000ULL),
.negedge_delay_ticks = (uint32_t)((uint64_t)DEADTIME_FALL_NS * timer_res_hz / 1000000000ULL),
.flags.invert_output = false,
};
// Apply deadtime using gen_a as the reference and gen_b as the complementary output
ESP_ERROR_CHECK(mcpwm_generator_set_dead_time(gen_a, gen_b, &dt_config));
// 7) Enable & start timer
ESP_ERROR_CHECK(mcpwm_timer_enable(timer));
ESP_ERROR_CHECK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP));
ESP_LOGI(TAG, "MCPWM started on GPIO%d (A) and GPIO%d (B)", PWM_GPIO_A, PWM_GPIO_B);
// If you want to change duty at runtime:
// mcpwm_comparator_set_compare_value(comparator, new_compare_ticks);
while (1) {
vTaskDelay(pdMS_TO_TICKS(1000));
}
}
🇯🇵 Vcc(24V)とMOSFETのDrain間に330Ωの抵抗体を入れた後に、ESP32マイコンのPWMピンの出力波形、一つのHalfbridgeMOSFETのV_GS波形もオシロスコープで測定しました。
🇬🇧 After inserting 330 Ω between Vcc(24 V) and MOSFET drain to prevent shootthrough overcurrent, I measured ESP32 MCU PWM output as well as one halfbridge MOSFET V_GS with the oscilloscope. The only output load is a 10 K resistor and LED pilot.
ESP32 PWM out (GPIO17 and GPIO18)
⚠️ It is critical to limit the current through MOSFETs with a resistor between the input power supply and drain of the MOSFET as long as there is the possibility of shoot-throught (same leg FET are ON simulatenously, creating a short circuit and damaging faster than the time the test power supply can react, if current is high enough. I put a 10 Ω 50 W resistor in my case (gold color in pictures below).
Halfbridge MOSFETs V_GS (high side MOSFET gate to GND voltage is orange line, low side MOSFET gate to GND voltage is blue line). Note that the oscilloscope does not allow two different voltage references simultaneously, so the the high side MOSFET is meaured as Gate to GND (not Gate to Source).
I set pull down resistors from Gate to Source of 20 kΩ. Below is the new waveform, this time the time horizon is 500 ns, so the overlap of rise/fall time and ringing of the gate voltage on both FETs of the halfbridge can be seen more clearly.
Even if the Miller plateau area of each MOSFET seems to be overlapping with each other, so maybe not full conduction mode, shoot through still happens. To prove that I measured voltage accross the 10 Ω resistor between Vcc and halfbridge MOSFET drain, which would result in V = 10 x I.
In the image above, it can be seen that there are some peaks of current, at the same frequency as the V_GS overlaps, proving some degree of shoothrough happens.
Also, I measured the high side MOSFET drain to GND during the full cycle, which should be always stable and close to Vcc (otherwise it means both high and low side MOSFET would be conducing simulatenously), and there indeed some voltage drops that look dangerous, as seen below. I also saw a little bit of smoke coming out from the PCB, though I could not pinpoint the exact part.
I decided to be more conservative, reducing the PWM frequency and increasing deadtime slightly for the next round of the halfbridge test.
I tried with 600 ns rise time and fall time, seeminly reduced the overlap slightly, and 1000 ns even more, to the point where only sometimes i can see high side FET drain to GND voltage drops, not in every switching.
After running for a few seconds without load, I saw the smoke again, and detected the bulk capacitor getting very hot. I realized the PWM output by the ESP32 was also heavily distorted, due to bugs during re-coding.
I recognized there are some incorrect points in the source code generated by OpenAI, where the ticking resolution was too small to produce a meaningful deadtime (rounded to 0). After many iterations, I re-generated the code as follows:
#include <stdio.h>
#include <inttypes.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_err.h"
#include "esp_log.h"
#include "driver/mcpwm_prelude.h"
static const char *TAG = "mcpwm_halfbridge";
// ===== USER SETTINGS =====
#define PWM_GPIO_A 17 // Output A
#define PWM_GPIO_B 18 // Output B
#define PWM_FREQUENCY_HZ 10000 // 10 kHz (use 10k for validation, then raise later)
#define PWM_DUTY 0.40f // 40%
#define TIMER_RES_HZ 5000000 // 5 MHz -> 200 ns / tick
#define DEADTIME_RISE_NS 900 // deadtime in ns
#define DEADTIME_FALL_NS 900
// =========================
static inline uint32_t ns_to_ticks(uint32_t ns, uint32_t timer_res_hz)
{
// ticks = ns * (ticks/sec) / 1e9
return (uint32_t)((uint64_t)ns * (uint64_t)timer_res_hz / 1000000000ULL);
}
void app_main(void)
{
ESP_LOGI(TAG,
"Start: f=%dHz duty=%.2f timer_res=%" PRIu32 "Hz deadtime=%" PRIu32 "ns/%" PRIu32 "ns",
PWM_FREQUENCY_HZ, (double)PWM_DUTY, (uint32_t)TIMER_RES_HZ,
(uint32_t)DEADTIME_RISE_NS, (uint32_t)DEADTIME_FALL_NS);
// ---- 1) Timer ----
mcpwm_timer_handle_t timer = NULL;
const uint32_t period_ticks = (uint32_t)(TIMER_RES_HZ / PWM_FREQUENCY_HZ);
if (period_ticks < 10) {
ESP_LOGE(TAG, "period_ticks too small (%" PRIu32 "). Lower PWM freq or increase TIMER_RES_HZ.", period_ticks);
abort();
}
mcpwm_timer_config_t timer_config = {
.group_id = 0,
.clk_src = MCPWM_TIMER_CLK_SRC_DEFAULT,
.resolution_hz = TIMER_RES_HZ,
.period_ticks = period_ticks,
.count_mode = MCPWM_TIMER_COUNT_MODE_UP,
};
ESP_ERROR_CHECK(mcpwm_new_timer(&timer_config, &timer));
// ---- 2) Operator ----
mcpwm_oper_handle_t oper = NULL;
mcpwm_operator_config_t oper_config = { .group_id = 0 };
ESP_ERROR_CHECK(mcpwm_new_operator(&oper_config, &oper));
ESP_ERROR_CHECK(mcpwm_operator_connect_timer(oper, timer));
// ---- 3) Comparator ----
mcpwm_cmpr_handle_t comparator = NULL;
mcpwm_comparator_config_t cmpr_config = {
.flags.update_cmp_on_tez = true, // safe updates at counter==0
};
ESP_ERROR_CHECK(mcpwm_new_comparator(oper, &cmpr_config, &comparator));
uint32_t compare_ticks = (uint32_t)((double)PWM_DUTY * (double)period_ticks);
if (compare_ticks == 0) compare_ticks = 1;
if (compare_ticks >= period_ticks) compare_ticks = period_ticks - 1;
ESP_ERROR_CHECK(mcpwm_comparator_set_compare_value(comparator, compare_ticks));
// ---- 4) Generators ----
mcpwm_gen_handle_t gen_a = NULL;
mcpwm_gen_handle_t gen_b = NULL;
mcpwm_generator_config_t gen_a_config = { .gen_gpio_num = PWM_GPIO_A };
mcpwm_generator_config_t gen_b_config = { .gen_gpio_num = PWM_GPIO_B };
ESP_ERROR_CHECK(mcpwm_new_generator(oper, &gen_a_config, &gen_a));
ESP_ERROR_CHECK(mcpwm_new_generator(oper, &gen_b_config, &gen_b));
// ---- 5) Define ONLY generator A waveform (raw PWM) ----
// A: HIGH at TEZ (counter=0), LOW at compare
ESP_ERROR_CHECK(mcpwm_generator_set_action_on_timer_event(
gen_a,
MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP,
MCPWM_TIMER_EVENT_EMPTY,
MCPWM_GEN_ACTION_HIGH)));
ESP_ERROR_CHECK(mcpwm_generator_set_action_on_compare_event(
gen_a,
MCPWM_GEN_COMPARE_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP,
comparator,
MCPWM_GEN_ACTION_LOW)));
// IMPORTANT: do NOT program gen_b actions here.
// Let the deadtime unit generate the paired (complementary) output.
// ---- 6) Deadtime ----
uint32_t dt_rise_ticks = ns_to_ticks(DEADTIME_RISE_NS, TIMER_RES_HZ);
uint32_t dt_fall_ticks = ns_to_ticks(DEADTIME_FALL_NS, TIMER_RES_HZ);
// Clamp deadtime so it cannot consume the pulse completely.
// Prevents "weird waveform" when dt is too large for duty/period.
if (dt_rise_ticks >= compare_ticks) {
dt_rise_ticks = (compare_ticks > 1) ? (compare_ticks - 1) : 0;
}
uint32_t off_ticks = period_ticks - compare_ticks;
if (dt_fall_ticks >= off_ticks) {
dt_fall_ticks = (off_ticks > 1) ? (off_ticks - 1) : 0;
}
ESP_LOGI(TAG,
"ticks: period=%" PRIu32 " compare=%" PRIu32 " dt_rise=%" PRIu32 " dt_fall=%" PRIu32,
period_ticks, compare_ticks, dt_rise_ticks, dt_fall_ticks);
mcpwm_dead_time_config_t dt_config = {
.posedge_delay_ticks = dt_rise_ticks,
.negedge_delay_ticks = dt_fall_ticks,
.flags.invert_output = true, // generate complementary output on B
};
ESP_ERROR_CHECK(mcpwm_generator_set_dead_time(gen_a, gen_b, &dt_config));
// ---- 7) Start ----
ESP_ERROR_CHECK(mcpwm_timer_enable(timer));
ESP_ERROR_CHECK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP));
ESP_LOGI(TAG, "Running: A=GPIO%d, B=GPIO%d", PWM_GPIO_A, PWM_GPIO_B);
while (1) {
vTaskDelay(pdMS_TO_TICKS(1000));
}
}
I retested with the gate driver on and Vcc 24 V at the halfbridge drain. Below each MOSFET gate voltage to GND.
Below it can be seen also de halfbridge high side drain to GND voltage, and the voltage drop at the 10 Ω input resistor as a current measurement proxy. There seems to still be some shoot-through, or at least some current through the body diode cause by Coss discharge and parasitic inductance happening, though just during low side MOSFET turn on and high side MOSFET turn off.
KEY finding: destructive behavior due to unstable high side MOSFET gate driving (Miller effect + ringing)
I did one more try (which had stop soon after I started as smoke came up again and the capacitor blew up, as it can be modestly seen in the picture below) measuring the high MOSFET V_DS (blue line, top) and V_GS (orange line, bottom). The V_GS has a huge bouncing, collapsing several times to 0 V just after turning on the high side MOSFET. See oscilloscope picture below.
I conclude that large dV/dt on high side V_DS created massive current spikes (large di/dt) for charging Coss that also forces a current on gate, which created that huge voltage bouncing. Classic failure when bringing up a half-bridge.
The displacement (Miller) current through the gate–drain capacitance is:
When the switching node moves very fast (large
On the high-side MOSFET, this current must return to the source (VS), so any impedance or inductance
in the gate–driver loop directly disturbs
Indeed, the large ringing observed at the high side MOSFET in the pictures above already hinted at it. I conclude that this issue is barely seen at the low side MOSFET as its source is directly connected to ground.
For the next test, I replaced the 44.8 kΩ Gate to Source resistor by a 1 kΩ resistor, in order to sink more current through the gate loop of the high side MOSFET. Below is my undertanding of the gate loop, which is actually several loops, one thorugh the gate driver VS→Drive→HO, then other through MOSFET Source→pull down resistor→MOSFET Gate.
10 kHzPWM 60%duty (6μs) ハイサイドFETのGateに1ｋΩPull downの実験結果は以下です。低周波数10ｋHz、広いパルズ幅でもBootstrapコンデンサ（V_GS）は完全に放電されなく、問題ないと判定しました。不安定、大きな電圧降下がほぼ直りましたが、何度も実験して、1回瞬時的な電圧効果を監察しました。
The halfbridge drain to GND voltage waveform become almost flat. After measuring the 10 Ω resistor from the power supply to the PCB Vcc, some current peaks are observed, which have a typical RC net charging current waveform (below picture). This assumed to be a healthy MOSFET Crss and Coss charging current.
I generated a new code with OpenAI to drive both halfbridges (full bridge) with a phase shift (skipped to make this article briefer).
Source code removed
Below is the halfbridge A HI and LI with FAN7382 powered on, Vcc = 24 V and the 10 Ω series resistor at Vcc input for limiting current. There is indeed some overlap which will cause shoothrough as well as signficant voltage spikes.
⚠️I tried regenerating the code with OpenAI for "must see" deadtime multiple times. Although ESP32 includes an MCPWM ‘dead-time’ feature, my measurements showed that complementary outputs were not consistently non-overlapping on both commutations under phase-shift/full-bridge style timing. Because shoot-through is destructive even for sub-µs overlap, I concluded that deadtime must be enforced by a controller/timer designed for power conversion (PSFB controller IC or motor-control PWM MCU).
Therefore, I decided to use a PWM control ASIC specific for full bridges. My choice was the Texas Instruments UCC3895, simply due to lack of stock or small number procurement possibilities for many others I considered.
ASIC control
UCCx895 datasheet contains some application diagrams, but I found it quite cryptic and just applicable to specific cases. Therefore, I created my own schematics using the UCC3895 (below) and used the internal block diagram of the UCC3895 to understand how it works. Below is my understanding and my initial design based on it.
Clock for generating PWM
UCCx895 has an RT port which generates a constant current (yellow arrow in my diagram) supply though the external RT resistor (82 kΩ in this case, as suggested in the datasheet).
This constant current is used for charging CT capacitor through CT port (green arrow in my diagram) until a certain voltage threshold. After, it is discharged almost inmediately through the internal resistor (purple arrow in my diagram).
This pattern created a sawtooth waveform voltage in CT capacitor, which I used as a ramp (connected to RAMP port, red dashed arrow in my diagram) so that the UCCx895 compares it with PI controller output signal for generating PWM.
PI controller
Current Sensor & Soft start
ASIC PCB board layout
Large copper pour as much as possible for Power Ground (PGND), start ground (all connected to a common point) for the other GND. PGND and GND common point connected as close as possible to the UCC3895 decoupling capacitor (-) terminal. This is to minimize the large di/dt in the high current traces (PGND) from inducing voltage spikes in the more sensitive ground traces.
I kept ceramic capacitors used for filtering and decoupling as close as possible to the UCC3895 pins.
OUTA, OUTB, OUTC, OUTD are traces with fairly high dv/dt since they are almost square signals. I tried to keep them not too close in distance from other traces since stray capacitances can induce displacement current and create cross-talking (EMI). Below the intial view of my prototype PCB created in EasyEDA.
Below the PCB with the PSFB ASIC in SMD soldered. I could solder it successfully by putting flux in both PCB pads and ASIC pin, pretinning one pad, fixing the ASIC using the pretinned pad and then adding a really tiny amount of soldering metal with iron tip (it worked even with a really thick iron tip). I later verified all connection between ASIC pins and PCB pads with a multimeter.
For C9 between /DISB pin and GND I used 2.2μF instead of 1μF, and on C1 I put 100 pF instead of 220 pF due to availability of components. Also for R5 = 68K instead of 82, and for R7 and R8 20K instead of 33.
ASIC control board bring up and debugging
以下がASIC基板の組立完了、メイン基板と繋げた状態で、UCC3895 ASIC のREF（オレンジ線）とCT（青線の波形）。オシロスコープの青い線は大きなマイナスオフセット誤差があることに注意する必要です。
REFは4.99Vに固定されています → ✅️
CT波形は約０V→約２V、約７μｓ周期Saw toothになります。 → ✅️
EAOUT電圧は0.149Vに固定されています。
EAN電圧は2.50V, EAP電圧は0V.
EANとEAPを逆に使っていたことを気づきました。正しい用途は、EAP目標電圧、EANはフェイドバック入力です。ケーブルと判断で基板を直し、EAOUTの電圧は4.5V以上に上がりました。
以下はOUTAとOUTBの波形です。上がり、下がりでもDeadtimeの周期（約0.5μs）も確認できました。
MOSFET full bridge + ASIC control
Below the two halfbridges MOSFET gate to ground voltage waveforms.
Gate resistors (R_G) are 10 Ω each.
For this test, I used a 10 Ω resistor between +24 V (Vcc) and the high side MOSFETs's drains. There is no load connected at the output of the full bridge (drains of both low side MOSFETs)
And below the voltage waveform of the output of the full bridge with a 220 Ω resistor connected as output load (between both low side MOSFETs's drains) instead of a transformer primary winding.
The 10 Ω resistor between +24 V (Vcc) and high side MOSFETs is still in place to prevent damage from a potential shoot-through.
PSFB + Transformer + Passive rectification
Provisional design
EPCOS B66325G0000X187 Transformer Ferrite Coreを購入、仮にトランスフォーマーを作り、一次側をMOSFETのFullBridge出力に繋げました。
Vin = 24 V
fsw = 100 kHz
Worst-case on-time:
t_on,worst = 1 / (2 × fsw)
t_on,worst = 1 / (2 × 100000) = 5 µs
Core effective area:
Ae = 178 mm² = 178 × 10⁻⁶ m²
Design flux density:
Bmax = 0.2 T
Primary Turns (Anti-Saturation Condition)
Flux equation:
Bpk = (Vpri × t_on) / (Np × Ae)
Rearranged for minimum primary turns:
Np ≥ (Vpri × t_on,worst) / (Bmax × Ae)
Substituting values:
Np ≥ (24 × 5 × 10⁻⁶) / (0.2 × 178 × 10⁻⁶)
Numerator:
24 × 5 × 10⁻⁶ = 120 × 10⁻⁶
Denominator:
0.2 × 178 × 10⁻⁶ = 35.6 × 10⁻⁶
Therefore:
Np ≥ (120 × 10⁻⁶) / (35.6 × 10⁻⁶) ≈ 3.37
Final result:
Np ≥ 4 turns
Transfomer output test
以下はトランスフォーマーとの直結0.1Ω（電流測定）抵抗体の電圧降下です。
二次側負荷無し、DCDC入力に10Ω抵抗体。
サージを除き、最大値は約+/-70 mVを確認できました（+/- 0.7 A)。周期は約6μsです。
✅️トランスフォーマーのコアーは飽和になっていません。
以下は同じ条件で一次側の電圧波形です。
二次側↓
Picture below shows the PSFB PCB, then ASIC control PCB and transformer all connected and ready to operate.
Full DC/DC converter output test
Condition: V_in 10 Ω R_limiter | No output load | C_out = 100 μF | N = 4 turns
Below picture shows the oscilloscope measuring one high side MOSFET V_GS (blue line) and V_DS (orange line). Even at almost no load (besides an LED with 5K resistor at the output), it can be seen that when switching on the MOSFET (V_GS rise edge, blue line), V_DS (orange) has already fallen and has some oscillations, looking to have achieved Zero Voltage Switching (ZVS).
Below is the DC/DC output voltage (blue line - fully flat, almost no ripple observed at this resolution) and the diode full bridge output before the LC (orange line).
Condition: R_limiter not connected | No output load | C_out = 100 μF | N = 4 turns
Almost the same results as in the test with the 10 Ω input current limiter, though this time, I can see some DC/DC output voltage transients (blue line, picture below).
Below pictures the equivalent to test before.
V_GS (blue) and V_DS (orange) of one high side MOSFET.
Transfomer primary winding low side current (R_sense is 0.1 Ω）
Condition: R_limiter not connected | 10 Ω output resistive load | C_out = 100 μF | N = 4 turns
Below pictures the equivalent to test before.
V_GS (blue) and V_DS (orange) of one high side MOSFET.
Transfomer primary winding low side current (R_sense is 0.1 Ω）. The load got really hot, so there is no doubts there is significant power/current through it.
There is no voltage ripple observed at the 10 Ω resistive load.
LTspiceによるZero Voltage Switching (ZVS)を再現
以下のモデルを立てて、IRFZ44N合計容量や抵抗値、20SQ045ジャンクション容量に近い部品を選択しました。
Investigating ZVS at apparently no load
I believe the ZVS without apparently any load was caused by a very large magnetizing current (reactive power) of the transfomer.
The lower the number of winding turns in the primary, the larger the magnetizing current is.
I did below measurements removing the load for the original transformer prototype and measured the current through a 0.1 ohm R_sense at the primary winding.
Transformer primary winding number of turn N = 4 (approx.)
Magnetizing current maximum value (excluding massive spikes) is measured to be around +/- 70〜80 mV → +/- 0.7〜0.8 A.
According to my calculations:
From core data (EPCOS N87):
A_L = 3950 nH (tolerance +30% / -20%)
L_M = A_L N_p^2
For N_p = 4 turns:
L_M = 3950 nH × 4^2
L_M = 3950 nH × 16
L_M ≈ 63 µH
ΔI_M = (V × t_on) / L_M = (24 V × 6 µs) / 63 µH = (24 × 6 × 10⁻⁶) / (63 × 10⁻⁶)
ΔI_M ≈ 2.28 A (peak-to-peak) I_M,peak ≈ 1.14 A
Considering:
- ±30% / −20% A_L tolerance
- Turn count variation
- Timing uncertainty
The calculated value is close to the experimentally observed current.
Transformer primary winding number of turn N = 10 (approx.)
Magnetizing current maximum value (excluding massive spikes) is measured to be around +/- 30〜40 mV → +/- 0.3〜0.4 A.
However, even with N=10 turns and lower magnetizing current, ZVS still happens without any output load (other than a simple LED indicator). As it can be seen in the oscilloscope screen image below, the difference in MOSFET V_DS (orange) voltage drop magnitude versus time does not differ noticeably compared to the case where the transformer had 4 turns and higher magnetizing current, and V_GS rising edge (switch on) happens after V_DS is around 0 V.
The output current measured with a similar 0.1 ohm resistor is as below (contaminated by spikes due to stray inductance and di/dt)
At 6.22 V and 0.58 A this would be a power at the output load of around 3.61 W.
This would result in an estimated efficiency of around 75%, indeed very low for almost any type of DC/DC converter, but it needs to be considered that it is likely low load, partly "affected by connecting 3 units of 0.1 ohm in series accross the DC/DC converter (1 between V+ input and inout capacitor, 1 at the low side of the transfomer primary winding, 1 at the output load high side) for current measurement. Perhaps even more importantly (to be confirmed later), the transformer is operating at >160 kHz and it is not using litz wire, so skin effect power losses are likely high).
Below is the current proxy measurement (0.1 ohm resistor voltage contaminated woth voktage transients due to di/dt and stray inductance) in blue color and the transformer primary voltage in orange (flipped upside down)
There is appoximately 0.6 to 0.7 A in the primary, which would cause power losses on this 0.1 ohm current measurement resistor as well. Since it is quite contaminated due to inductances and voktage spikes, I will assume the average current on the transformer is the same as measured at the input of the DC/DC converter.
P_loss_R1 = (0.2 A)^2 × 0.1 = 0.004
P_loss_R2 = 0.004
P_loss_R3 = (0.58 A)^2 × 0.1 = 0.0336 W
Summing up 0.0344 W in total, which is not an actual power loss of the DC/DC converter itself, which still not so meaningful comapred to the more than 4 of operation.
The MOSFET seems to still be achieving ZVS as seen below (orange is V_DS, blue is V_GS)
The rectification diodes have voltage drop when not conducing of 0.08 V to 0.12 V. At 0.58 A, each one would be losing 0.0464 W to 0.0696 W, which in total would be more than 0.1 W, this is a major contributor to power losses and low efficiency.
Power losses at no-load conditions
When the output load is disconnected (only the indicator LEDs, limiter resistors, and the output LC filter remain connected):
This represents the approximate fixed power consumption of the converter under these operating conditions (magnetizing current, MOSFET switching losses, copper losses, LM317 regulator dissipation, control IC and gate drivers, and auxiliary loads).
This represents the fixed power consumption of the converter in this operating condition, which includes:
- magnetizing current of the transformer
- MOSFET switching and conduction losses
- copper losses in traces and windings
- LM317 regulator dissipation
- UCC3895 controller consumption
- gate driver power
- LED indicators and limiter resistors
Identified major power losses to components
I did a quick finger touch test to quickly identify which components are at high temperature after a 2 or 3 minutes test at 0.4 A input current, 23.6 V.
The hottest component was the LM317 (without and with heatsink attached), which like a very mild burning after 5 to 10 seconds (as long as the heatsink is not attached). It has a input voltage of 23.6 V, and output voltage of 11.5 V. It is powering the UCC3895DW (typical consumption of 5 mA) and the 4 gate drivers FAN7382 / IRFZ44N MOSFETs gate. Rectification Shottky diodes and MOSFETs just presented a very mild temperature increase, same for output capacitor (electrolytic only at the moment). Transformer ferrite core, windings, input capacitors and LEDs (green LED connector to ouput voltage with a 5 K resistor in series and blue LED connected to input voltage with a 10 K resistor in series) semt to have no noticeable temperature increase.
The MOSFET gate drive alone can dissipate approximately 0.5 W in the LM317 regulator, based on voltage drop accross the LDO LM317 and consumption of the gate driver/MOSFET loop.
With just a 100 μF electrolytic (high ESR) capacitor at the output:
V_out = 3.78 V, R_load = 3.0 Ω, V_in = 23.6 V, I_in = 0.410 A
With a 10 μF ceramic + 250 μF electrolityc (low ESR):
V_out = 3.744 V, R_load= 3.0 Ω, V_in = 23.6 V, I_in = 0.407 A
✅ The output capacitor is unlikely to be a very siginificant factor of power losses.
The secondary winding number of turns increased sligthly (around 1 and half more) to increase output voltage. I did two more tests.
| Case | Vin [V] | Iin [A] | Pin [W] | Vload [V] | Rload [Ω] | Pout [W] | Efficiency |
|---|---|---|---|---|---|---|---|
| 1 | 23.84 | 0.501 | 11.94 | 7.38 | 6 | 9.08 | 76.0% |
| 2 | 17.95 (voltage derating) | 0.623 (PSU limited to 0.5 A | 11.18 | 5.01 | 3 | 8.37 | 74.8% |
Efficiency increased further to 76.0%. This is likely due to rectification diodes wasting less power due to less current to the load, keeping nearly equal to tests before due to higher voltage.
Heating and temperature verification
Component temperatures were measured using an infrared thermometer (Ketotek KT600Y).
The converter was operated with a 6 Ω load.
Operating conditions:
V_{in}=23.82\ \mathrm{V} I_{in}=0.505\ \mathrm{A} V_{load}=7.34\ \mathrm{V} I_{out,estimated}=1.22\ \mathrm{A}
The input current slightly increased from 0.495 A to 0.505 A after several minutes of operation, likely due to temperature rise of some components.
Measured temperatures
| Component | Temperature |
|---|---|
| Load resistor | 105 °C |
| High-side MOSFET heatsink | 33 °C |
| Low-side MOSFET heatsink | 40 °C |
| Input electrolytic capacitor | 30 °C |
| Output filter inductor | 32 °C |
| Schottky rectifier diodes | 50 °C |
| LM317 heatsink | 39 °C |
| Output electrolytic capacitor | 30 °C |
| Transformer winding | 29 °C |
| Control ASIC / control board | 27 °C |
| Laboratory power supply case | 50 °C |
The load resistor reaches the highest temperature (about 105 °C), which is expected since it dissipates most of the output power.
Among the converter components, the Schottky rectifier diodes exhibit the highest temperature (~50 °C), indicating that rectifier conduction losses are likely one of the dominant loss mechanisms in the present prototype.
The MOSFET heatsinks remain relatively cool (33–40 °C), which is consistent with the observation of near-ZVS switching, resulting in low switching losses.
The transformer and inductive components remain close to ambient temperature, suggesting that magnetic and copper losses in these components are moderate at this operating point.
Efficiency and temperature at medium load (3Ω, 6Ω）
Below a test setup with a STP6005D power supply capable of 60 V and 5 A.
|
|
|
|
|
Load [ |
|
|
|
|
Thermal |
|---|---|---|---|---|---|---|---|---|---|
| 30.0 | 0.66 | 19.8 | 9.55 | 6 | 1.59 | 15.20 | 4.60 | 76.8 | Diode: 50°C, LM317: 43°C |
| 35.0 | 0.76 | 26.6 | 11.19 | 6 | 1.87 | 20.87 | 5.73 | 78.5 | — |
| 40.0 | 0.88 | 35.2 | 12.89 | 6 | 2.15 | 27.69 | 7.51 | 78.7 | Diodes: ~60°C, LM317: ~40°C |
| 40.0 | 1.47 | 58.8 | 11.85 | 3 | 3.95 | 46.80 | 12.0 | 79.6 | Diodes: 65–67°C |
- Efficiency increases with load and stabilizes around ~79–80%
- Losses scale with power → conduction losses dominate
- Schottky diodes are the main thermal bottleneck
- LM317 thermal impact is relatively small
Transformer Behavior
Primary current waveform remains approximately linear (no sharp slope increase):
→ No clear indication of core saturation at these operating points
Efficiency measurement (1 Ω load, high current)
I performed an additional measurement using a very low load resistance.
| Parameter | Value |
|---|---|
| Vin | 24.0 V |
| Iin | 1.56 A |
| Pin | 37.44 W |
| Vout | 4.78 V |
| Iout | 4.737 A |
| Pout | 22.64 W |
| Load | 1 Ω |
| Efficiency | 60.5 % |
The efficiency was calculated as:
Pin = Vin × Iin = 24.0 × 1.56 = 37.44 W
Pout = Vout × Iout = 4.78 × 4.737 ≈ 22.64 W
Efficiency ≈ 22.64 / 37.44 ≈ 60.5 %
With a 1 Ω load the secondary current becomes very high (~4.7 A). The output voltage drops to 4.78 V, which indicates the converter is operating outside the optimal regulation region. The reduced efficiency is likely due to increased conduction losses in the transformer, rectifier diodes, and MOSFETs.
| Parameter | Value |
|---|---|
| Vin | 30.0 V |
| Iin | 1.98 A |
| Pin | 59.4 W |
| Vout | 6.07 V |
| Iout | 6.004 A |
| Pout | 36.45 W |
| Load | 1 Ω |
| Efficiency | 61.4 % |
Efficiency ≈ 36.45 / 59.4 ≈ 61.4 %
The output current increases to approximately 6 A with the 1 Ω load. The output voltage rises to 6.07 V, but the converter still operates outside the optimal regulation region.
The rectifier diodes reached a maximum temperature of 92 °C, indicating that diode conduction losses are a major contributor to the efficiency limitation at this load current.
I performed another measurement increasing the input voltage while keeping the same 1 Ω load.
| Parameter | Value |
|---|---|
| Vin | 35.0 V |
| Iin | 2.37 A |
| Pin | 82.95 W |
| Vout | 7.16 V |
| Iout | 7.108 A |
| Pout | 50.88 W |
| Load | 1 Ω |
| Efficiency | 61.3 % |
Efficiency ≈ 50.88 / 82.95 ≈ 61.3 %
The rectifier diodes reached a maximum temperature of 96 °C, confirming that diode conduction losses become significant at high output currents.
| Parameter | Value |
|---|---|
| Vin | 37.9 V |
| Iin | 2.81 A |
| Pin | 106.50 W |
| Vout | 7.76 V |
| Iout | 7.76 A |
| Pout | 60.22 W |
| Load | 1 Ω |
| Efficiency | 56.5 % |
Efficiency ≈ 60.22 / 106.50 ≈ 56.5 %
With the 1 Ω load the output current increases to approximately 7.8 A. The output voltage rises to 7.76 V, but the converter is operating far from the nominal regulation point.
During this test very large voltage ringing was observed across the rectification diodes, which suggests significant leakage inductance in the transformer and high di/dt switching currents. This ringing likely contributes to additional switching losses and reduced efficiency at higher input voltage.
I observed a very large voltage ringing across rectification diodes, though the output voltage shows very little. Below pictures.
Summary of efficiency measurements
|
|
|
|
|
Load [ |
|
|
Efficiency | Observations |
|---|---|---|---|---|---|---|---|---|
| 17.95* | 0.623 | 11.18 | 5.01 | 3 | 1.67 | 8.37 | 74.8 % | PSU current limited to 0.5 A (voltage derating). |
| 23.84 | 0.501 | 11.94 | 7.38 | 6 | 1.23 | 9.08 | 76.0 % | Moderate load test. |
| 24.0 | 1.56 | 37.44 | 4.78 | 1 | 4.74 | 22.64 | 60.5 % | High current; rectifier conduction losses increase. |
| 30.0 | 1.98 | 59.40 | 6.07 | 1 | 6.00 | 36.45 | 61.4 % | Heavy load; diode heating and switching stress increase. |
| 35.0 | 0.76 | 26.60 | 11.19 | 6 | 1.87 | 20.87 | 78.5 % | Transformer current ramp linear; no saturation signs. |
| 35.0 | 2.37 | 82.95 | 7.16 | 1 | 7.11 | 50.88 | 61.3 % | Heavy load; rectifier losses dominant. |
| 37.9 | 2.81 | 106.50 | 7.76 | 1 | 7.76 | 60.22 | 56.5 % | Strong ringing across rectifier diodes observed. |
| 40.0 | 1.47 | 58.80 | 11.85 | 3 | 3.95 | 46.80 | 79.6 % | Diodes 65–67 °C; stable operation near ~47 W output. |
Below graph shows efficiency vs output current (including load resistance)
Ringing at rectification diodes likely increases power losses at high current
A large fraction is due to the schottky diode full bridge rectifier, as I estimate in beliw table.
Estimated Schottky rectifier losses in the 1 Ω tests
For the full diode bridge, two Schottky diodes conduct simultaneously.
Using a typical forward voltage of V_f=0.35 and a maximum forward voltage of V_f=0.55:
|
|
|
|
Efficiency |
|
|
|
|---|---|---|---|---|---|---|
| 24.0 | 4.737 | 37.44 | 60.5 % | 14.79 | 3.32 | 5.21 |
| 30.0 | 6.004 | 59.40 | 61.4 % | 22.93 | 4.20 | 6.60 |
| 35.0 | 7.108 | 82.95 | 61.3 % | 32.10 | 4.98 | 7.82 |
| 37.9 | 7.760 | 106.50 | 56.5 % | 46.33 | 5.43 | 8.54 |
The estimated Schottky bridge conduction losses become significant at high output current, but they do not by themselves explain the full measured loss in the 1 Ω tests.
Diodes maximum temperature measured with IR was around 96 ℃ at around 7 A. Typical thermal resistance junction to air (RΘJA) is 40 ℃/W. Assuming atemperature of air around the diode of 36 ℃, this would be around (96-32)/40 = 1.5 W roughly per diode. Muliplying by the four diodes, roughly 6 W of losses in the rectifier bridge seem plausible.
Breakdown of measured conduction losses (7.96 A output current test)
The following voltage drops were measured across different sections of the power path using a DMM.
Load current was approximately 7.96 A.
| Location | Measured voltage drop | Current | Estimated power loss | Comment |
|---|---|---|---|---|
| PSU + to PCB Vcc | 0.014 V | 2.64 A | 0.037 W | Small loss in supply wiring |
| PSU − to PCB GND | 0.040 V | 2.64 A | 0.106 W | Slightly higher due to return wiring |
| Input Vcc to HS input capacitor | ~0 V after stabilization | 2.64 A | negligible | Measurement drifted but stabilized near zero |
| Input GND to LS input capacitor | ~0 V | 2.64 A | negligible | Likely negligible copper loss |
| Input capacitor to HS MOSFET drain | ~0 V | — | negligible | No significant drop observed |
| HS MOSFET pair | — | — | not measurable | Switching node, oscilloscope shows ringing |
| HS MOSFET to transformer primary | — | — | unreliable | AC node, DMM not suitable |
| Transformer primary winding | — | — | not measurable, AC current measurement attempt failed | Requires separate estimation |
| Transformer secondary winding | — | — | not measurable | AC waveform prevents simple measurement |
| Rectifier diodes | — | ~7.96 A | 5.4–8.4 W (estimated) | Dominant loss source |
| Rectifier output to output capacitor (across inductor path) | 0.177 V | 7.96 A | 1.37 W | Significant copper / inductor path loss |
| Output capacitor HS to load + | 0.056 V | 7.96 A | 0.446 W | Wiring / PCB trace loss |
| Output capacitor LS to load − | 0.016 V | 7.96 A | 0.12 W | Minor return path loss |
| Output capacitor LS to rectifier return | 0.19–0.21 V | 7.96 A | 1.5–1.65 W | Significant copper loss |
The measurements show that the dominant power losses at high load are located in the rectification stage and the high-current copper paths between the rectifier, output capacitor, and load.
Estimated losses include:
- Rectifier diodes: approx. 5～8 W
- Copper losses in rectifier/output path: approx. 3 W
By comparison, losses in the PSU wiring and input path are very small (<0.2 W).
The measurements also highlight the limitations of using a DMM in switching nodes.
Voltage drops across MOSFETs and transformer windings could not be reliably measured due to the high-frequency switching waveforms and ringing.
For the 0.1 ceramic resistor for current measurement in series with the transforme, based on a simple resistive loss estimate, the expected power loss was relatively small:
I ≈ 2.8 A
P = I²R ≈ (2.8)² × 0.1 ≈ 0.8 W
Efficiency measurement for comparing with and without current measurement resistor (1 Ω load)
| Condition |
|
|
|
|
Efficiency |
|---|---|---|---|---|---|
| With 0.1 Ω → Without 0.1 Ω | 5.53 → 5.66–5.68 | 44.25 → 45.50 | 1.77 → 1.82 | 30.58 → 32.0–32.3 | 69.1 % → 70.4–70.9 % |
The voltage waveform on transformer does not appear to change significantly.
Rather than a large drop in efficiency, adding the 0.1 ohm resistor at the primary side seems to affect the operating output voltage and input current noticeably.
Overall, the data suggests that rectification losses and high-current copper paths dominate the efficiency reduction at high output current, while input wiring losses remain negligible.
Efficiency measurements (old DIY transformer)
Efficiency measurement (1 Ω load, current sense resistor removed)
| Vin [V] | Iin [A] | Pin [W] | Vout [V] | Iout [A] | Pout [W] | Efficiency |
|---|---|---|---|---|---|---|
| 15.0 | 1.01 | 15.15 | 3.19 | 3.19 | 10.19 | 67.3 % |
| 20.0 | 1.39 | 27.80 | 4.40 | 4.40 | 19.36 | 69.6 % |
| 25.0 | 1.80 | 45.00 | 5.67 | 5.67 | 32.15 | 71.4 % |
| 30.0 | 2.64 | 79.20 | 7.46 | 7.46 | 55.65 | 70.3 % |
| 32.2 | 2.82 | 90.80 | 7.98 | 7.98 | 63.68 | 70.1 % |
| 35.0 | 3.17 | 110.95 | 8.76 | 8.76 | 76.74 | 69.2 % |
| 39.0 | 3.63 | 141.57 | 9.70 | 9.70 | 94.09 | 66.5 % |
Efficiency increases with output power and stabilizes around 70%, decreasing slightly at higer power. Textbook like efficiency curve.
The trend above strongly suggests that there is no efficiency limitation due to low power, and that a big contributor, besides the rectifier diodes and to a smaller degree copper losses on rectifier, the transformer and its AC wires (difficult to measure power losses) are likely the main driver and the next point to tackle in a new development iteration.
Transformer redesign and impact on DC/DC operation
The leakage inductance of the secondary winding can be estimated based on the voltage ringing frequency on the rectifier, taking the schottky diode capacitance (tipically 1300 pF for 20SQ045)
It was observed that the transformer used previoulsy in test had some of its windings crossing each other due to poor construction. It had the primary and secondary windings interleaved.
Using exactly the same cables (same length), the transformer was winded considerably more neatly but without interleaving. See picture below.
| Vin [V] | Iin [A] | Pin [W] | Vout [V] | Iout [A] | Pout [W] | Efficiency |
|---|---|---|---|---|---|---|
| 15.0 | 0.94 | 14.10 | 3.05 | 3.05 | 9.30 | 66.0 % |
| 20.0 | 1.33 | 26.60 | 4.24 | 4.24 | 17.98 | 67.6 % |
| 25.0 | 1.71 | 42.75 | 5.46 | 5.46 | 29.81 | 69.7 % |
Although output voltage slighly decreased, it can be concluded that the transformer rewinding barely improved or reduced efficiency. Pressing with force the two EPCOS cores together did not noticeably changed input current nor output voltage, so it can be concluded that no there is unlikely any major air gap.
Shortening the transformer connections, non interleaved DIY transformer
The copper losses in the transformer windings and in the wires between the transformer and the PCB are believed to be major contributors to the total losses. To further evaluate this, the primary and secondary winding connections to the PCB (high AC current path) were shortened by about 10 cm, and the DC/DC efficiency was measured again under the same conditions as before.
| Vin [V] | Case | Iin [A] | Pin [W] | Vout [V] | Pout [W] | Efficiency |
|---|---|---|---|---|---|---|
| 15.0 | Original | 1.01 | 15.15 | 3.19 | 10.19 | 67.3 % |
| 15.0 | Secondary shortened | 1.00 | 15.00 | 3.13 | 9.80 | 65.3 % |
| 15.0 | Primary and secondary shortened | 0.98 | 14.70 | 3.09 | 9.55 | 65.0 % |
| --- | --- | ---: | ---: | ---: | ---: | ---: |
| 20.0 | Original | 1.39 | 27.80 | 4.40 | 19.36 | 69.6 % |
| 20.0 | Secondary shortened | 1.39 | 27.80 | 4.36 | 19.01 | 68.4 % |
| 20.0 | Primary and secondary shortened | 1.35 | 27.00 | 4.29 | 18.40 | 68.1 % |
| --- | --- | ---: | ---: | ---: | ---: | ---: |
| 25.0 | Original | 1.80 | 45.00 | 5.67 | 32.15 | 71.4 % |
| 25.0 | Secondary shortened | 1.77 | 44.25 | 5.57 | 31.02 | 70.1 % |
| 25.0 | Primary and secondary shortened | 1.72 | 43.00 | 5.49 | 30.14 | 70.1 % |
Shortening the transformer connections (both secondary and primary) did not improve efficiency. Shortening the wires did not produce a clear efficiency improvement, and the small differences observed are likely within the range of measurement uncertainty and operating-point and thermal variation. I hypothesized that reducing the wire by 20 cm in total could have significantly decreased inductance between MOSFETs source and transformer, affecting ZVS negatively. However, when I tried to measure with my oscilloscope V_DS and V_GS overlap (below), the waveformed seemed implausible and concluded that the noise coupling in the oscilloscope distorts the measurement critically, so the loss of ZVS hypothesis could not be confirmed.
⚠️ Heavily affected and distorted by noise coupling.
To prove the noise coupling in the oscilloscope is heavily affecting, I disconnected the probe ground crocodile and connect only the + side of the probe to MOSFET drain and gate. As seen below, even in this case the voltage waveform measured is huge and consistent with MOSFET switching dv/dt, proving that noise coupling is extremely high.
Although the rewound transformer has a cleaner mechanical structure, it does not include interleaving between primary and secondary windings.
In contrast, the previous transformer, despite being mechanically less organized, included partial interleaving.
Transformer interleaving and impact on DC/DC operation
The transformer was rewound using an interleaved structure:
- primary (half) on top
- secondary in the middle
- primary (half) on the bottom
The external connections were kept short. One connection between the two primary halves required an additional crossing turn, which was slightly loose.
| Vin [V] | Iin [A] | Pin [W] | Vout [V] | Iout [A] | Pout [W] | Efficiency |
|---|---|---|---|---|---|---|
| 15.0 | 1.26 | 18.90 | 3.57 | 3.57 | 12.75 | 67.5 % |
| 20.0 | 1.76 | 35.20 | 4.95 | 4.95 | 24.50 | 69.6 % |
| 25.0 | 2.26 | 56.50 | 6.31 | 6.31 | 39.82 | 70.5 % |
Although the output voltage increased compared with previous tests, this is likely influenced by a slightly different effective turns ratio, which is difficult to reproduce exactly in a manually wound transformer.
Therefore, this result does not allow a clear conclusion that interleaving improved efficiency. In fact, the measured efficiency at 25 V input is slightly lower than the previously measured 71.4 %.
Twisting / bundling the transformer connection wires
The wires between the PCB and the transformer were routed closer together and slightly twisted in order to reduce loop area and observe whether the DC/DC behavior changes and whether common-mode noise may be reduced.
| Vin [V] | Iin [A] | Pin [W] | Vout [V] | Iout [A] | Pout [W] | Efficiency |
|---|---|---|---|---|---|---|
| 20.0 | 1.76 | 35.20 | 4.94 | 4.94 | 24.40 | 69.3 % |
| 25.0 | 2.26 | 56.50 | 6.29 | 6.29 | 39.56 | 70.0 % |
Despite bundling and twisting connection cables, there is still huge noise coupling in the oscilloscope when measuring the MOSFETs.
Reducing primary turns and impact on efficiency
The primary winding was reduced step by step while keeping the same secondary winding. The initial configuration was approximately 9:3, then reduced to 8:3 and 7:3.
Load: 1 Ω
| Ratio (Np:Ns) | Vin [V] | Iin [A] | Pin [W] | Vout [V] | Iout [A] | Pout [W] | Efficiency |
|---|---|---|---|---|---|---|---|
| 9:3 | 15.0 | 1.26 | 18.90 | 3.57 | 3.57 | 12.75 | 67.5 % |
| 8:3 | 15.0 | 1.60 | 24.00 | 4.04 | 4.04 | 16.32 | 68.0 % |
| 7:3 | 15.0 | 2.00 | 30.00 | 4.51 | 4.51 | 20.34 | 67.8 % |
| 9:3 | 20.0 | 1.76 | 35.20 | 4.95 | 4.95 | 24.50 | 69.6 % |
| 8:3 | 20.0 | 2.19 | 43.80 | 5.50 | 5.50 | 30.25 | 69.1 % |
| 7:3 | 20.0 | 2.76 | 55.20 | 6.16 | 6.16 | 37.95 | 68.8 % |
Reducing the primary turns decreases the magnetizing inductance (
⚠️It is likely that the winding loosens and slightly changes its shape while reducing the number of turns, which also may affect the result.
⚠️The increase in output voltage is assumed to be positive for effciency due lower losses on the rectificacion diodes and copper, which also plays a role, so the results above have to be taken with caution.
Twisted two-strand transformer wiring and 6:2 turns ratio
The previous thick cable was replaced by two thinner twisted strands.
The approximate transformer turns ratio is now 6:2.
Load: 1 Ω
| Vin [V] | Iin [A] | Pin [W] | Vout [V] | Iout [A] | Pout [W] | Efficiency |
|---|---|---|---|---|---|---|
| 15.0 | 0.71 | 10.65 | 2.47 | 2.47 | 6.08 | 57.1 % |
| 20.0 | 1.13 | 22.60 | 3.78 | 3.78 | 14.27 | 63.1 % |
| 25.0 | 1.51 | 37.75 | 4.98 | 4.98 | 24.80 | 65.7 % |
| 30.0 | 1.86 | 55.80 | 6.10 | 6.10 | 37.21 | 66.7 % |
| 35.0 | 2.22 | 77.70 | 7.10 | 7.10 | 50.41 | 64.9 % |
| 40.0 | 2.86 | 114.40 | 7.60 | 7.60 | 57.76 | 50.5 % |
🔥At 40 V input the power supply shut down unexpectedly after some seconds. This likely indicates overcurrent protection, excessive transient current, or unstable operation due to increased circulating current / saturation margin reduction.
Damaging the MOSFETs after reducing primary turns
After the fault in the last test, the bench power supply triggered current limit even at very low input voltage.
In-circuit measurements showed approximately ~1 Ω or lower resistance between MOSFET drain and source, and an abnormally low diode reading (~0.02 V).
This strongly suggests that one or more MOSFETs were damaged, likely due to excessive circulating current or transient stress after reducing the primary turns too much.
The actual circulating current is higher due to freewheeling and parasitic effects, which likely contributed to MOSFET overstress.
Reducing the primary turns is a well-known failure mode in isolated DC/DC converters. It decreases magnetizing inductance, increasing circulating and magnetizing currents. This can quickly lead to excessive current stress, loss of safe operating margins, and MOSFET failure, even if the converter previously operated correctly at similar voltage and frequency.
I tried to reproduce the failure in LTspice. Below a simulation comparison between 190μH and 84μH magnetizing inductance at 25 V input, 1 Ω load.
V_in = 25 V, L_M = 190 μH, 6:2 turns ratio ↓
V_in = 25 V, L_M = 84 μH, 6:2 turns ratio ↓
V_in = 40 V, L_M = 84 μH, 6:2 turns ratio ↓
V_in = 40 V, L_M = 84 μH, 6:2 turns ratio, input bulk capacitor C=50μF & ESR=1Ω in parallel with C=1μF & ESR=1mΩ ↓
Plot of I(D3), simulated current accross the HS MOSFET body diode
V_in = 40 V, L_M = 190 μH, 6:2 turns ratio, input bulk capacitor C=50μF & ESR=1Ω in parallel with C=1μF & ESR=1mΩ ↓
V_in = 25 V, L_M = 84 μH, 6:2 turns ratio, input bulk capacitor C=50μF & ESR=1Ω in parallel with C=1μF & ESR=1mΩ. ↓
Plot of I(D3), simulated current accross the HS MOSFET body diode
💡 According to the LTspice simulation (with limited similarity with the real hardware), the current peak amplitude through the MOSFETs
It is needed to remove 2 or 3 of the MOSFETs from the PCB to check them individually. 2 of them had the body diode showing 0.0 V measured with the DMM (damaged), 2 of them had a body diode of 0.49 V (OK).
Transformer redesign with 1 mm diam. enamel wire
A new transformer was wound using thicker enamel wire to reduce copper losses and improve current handling.
- Primary: 12 turns, single strand (1 mm enamel wire)
- Secondary: 3 turns, two parallel strands (1 mm enamel wire, loosely twisted)
- Non-interleaved winding
The parallel secondary strands were not tightly fixed, which resulted in noticeable audible noise due to mechanical vibration under high AC current.
Efficiency measurement (1 Ω load, initial test)
When tested with a 1 Ω load, a very strong audible noise appeared immediately, and the PSU entered current limit. This behavior was not reproducible at no load, suggesting a high-current-related effect rather than a permanent short.
💡 Loose parallel secondary strands can produce strong audible noise due to magnetic forces.
Retest with 6 Ω load, ⚠️6 Ω limiting resistor on Vcc⚠️, and 0.1 Ω current sense resistor on primary winding
⚠️A 6 Ω series resistor was present at Vcc, so the actual converter input voltage was corrected as:
The estimated output power was calculated as:
and the estimated efficiency as:
| Vin (PSU) [V] | Iin [A] | Vin (conv) [V] | Pin (conv) [W] | Vout [V] | Pout [W] | Efficiency |
|---|---|---|---|---|---|---|
| 15.0 | 0.19 | 13.86 | 2.63 | 3.11 | 1.61 | 61.2 % |
| 20.0 | 0.26 | 18.44 | 4.79 | 4.32 | 3.11 | 64.9 % |
| 25.0 | 0.32 | 23.08 | 7.39 | 5.51 | 5.06 | 68.5 % |
| 30.0 | 0.39 | 27.66 | 10.79 | 6.70 | 7.48 | 69.4 % |
| 35.0 | 0.45 | 32.30 | 14.54 | 7.90 | 10.40 | 71.6 % |
| 40.0 | 0.51 | 36.94 | 18.84 | 9.09 | 13.77 | 73.1 % |
| 35.0 | 0.45 | 15.75 | 7.90 | 1.32 | 10.40 | 66.0 % |
| 40.0 | 0.51 | 20.40 | 9.09 | 1.52 | 13.77 | 67.5 % |
Efficiency measurement (6 Ω load, ✅️no input limiter, no current sense resistor)
| Vin [V] | Iin [A] | Pin [W] | Vout [V] | Iout [A] | Pout [W] | Efficiency |
|---|---|---|---|---|---|---|
| 15.0 | 0.21 | 3.15 | 3.43 | 0.57 | 1.96 | 62.2 % |
| 20.0 | 0.28 | 5.60 | 4.71 | 0.79 | 3.70 | 66.1 % |
| 25.0 | 0.35 | 8.75 | 6.01 | 1.00 | 6.02 | 68.8 % |
| 30.0 | 0.42 | 12.60 | 7.31 | 1.22 | 8.91 | 70.7 % |
| 35.0 | 0.49 | 17.15 | 8.59 | 1.43 | 12.30 | 71.7 % |
| 40.0 | 0.56 | 22.40 | 9.90 | 1.65 | 16.34 | 73.0 % |
Efficiency measurement (1 Ω load, no input limiter)
| Vin [V] | Iin [A] | Pin [W] | Vout [V] | Iout [A] | Pout [W] | Efficiency |
|---|---|---|---|---|---|---|
| 15.0 | 0.59 | 8.85 | 2.29 | 2.29 | 5.25 | 59.3 % |
| 20.0 | 0.81 | 16.20 | 3.25 | 3.25 | 10.56 | 65.2 % |
| 25.0 | 1.04 | 26.00 | 4.16 | 4.16 | 17.31 | 66.6 % |
| 30.0 | 1.27 | 38.10 | 5.10 | 5.10 | 26.01 | 68.3 % |
| 35.0 | 1.48 | 51.80 | 6.03 | 6.03 | 36.36 | 70.2 % |
| 40.0 | 1.71 | 68.40 | 6.90 | 6.90 | 47.61 | 69.6 % |
| 45.0 | 1.95 | 87.75 | 7.73 | 7.73 | 59.75 | 68.1 % |
| 48.0 | 2.17 | 104.16 | 8.22 | 8.22 | 67.57 | 64.9 % |
Despite lower magnetizing current and theretically better suited winding material, there is no clear improvement in efficiency of the transformer with double strand secondary winding, single strand primary winding, 1 mm diameter enamel wire compared to previous DIY transformer.
Temperature at high power with 12:3 enamel 1 mm diam.
A test was performed for several minutes at approximately 42 V input and 1 Ω load, while component temperatures were measured using a KT600Y IR thermometer.
The enamel wire surfaces heat up more visibly than the thick insulated generic cables used previously, so the temperature observation is more meaningful for this transformer version.
Measured temperatures:
- Rectifier diodes: 90–100 °C
- Transformer primary winding: ~40 °C
- Transformer secondary winding: ~50–60 °C
The secondary wires connecting the transformer to the PCB also became very warm, in some locations even more than the wires directly wound on the ferrite core. Since the ferrite-side wire surface is small, the IR reading there is less reliable.
These observations suggest significant conduction losses on the high-current AC secondary path, including:
- transformer secondary winding
- transformer-to-PCB wires
- likely PCB copper traces. As seen in the picture below, there is 50 mm x 3 mm thick and 70 mm x 3 mm
巻線構成比較（1 Ω負荷）
本検証では、巻線構成のみ変更し比較した。記載の線径はすべて**直径（diameter）**であり断面積ではない。
| 構成 | Vin [V] | Iin [A] | Vout [V] | η |
|---|---|---|---|---|
| 二次: φ0.26 mm ×7（並列・非撚り）一次: φ1 mm単線 | 20 | 0.80 | 3.23 | 65.1% |
| 30 | 1.27 | 5.12 | 68.8% | |
| 40 | 1.72 | 6.97 | 70.6% | |
| 二次: φ0.26 mm ×10（撚り）一次: φ1 mm単線 | 20 | 0.75 | 3.09 | 63.5% |
| 30 | 1.17 | 4.88 | 67.8% | |
| 40 | 1.57 | 6.59 | 69.2% | |
| 二次: φ0.26 mm ×10（撚り）一次: φ0.26 mm ×5（並列） | 20 | 0.73 | 3.06 | 63.9% |
| 30 | 1.13 | 4.82 | 68.5% | |
| 40 | 1.50 | 6.47 | 69.8% |
結論：細線多並列は有効だが、過度な本数増加や撚りにより巻線が太くなると結合が悪化し、効率は改善しない。
一次側巻線数12でもZVS発生
低い入力電圧（12V）状況で一次側巻線数を１２にしても負荷無し状況でZero Voltage Switching(ZVS)はまだ発生します。以下写真のオレンジ線はハイサイドMOSFET
PSUで測定電流は0.04Aに達しました。
LTspiceによる再現してみました。以下はLTspice回路と波形（白色Id1はHS-MOSFETの電流になります。オレンジ色はV_GS、青色はV＿DS（以上写真と同じ）。IRFZ44Nと同じような容量と抵抗値SUD40N10-25、20SQ045と同じようなC_J（寄生容量）MBRS340を利用しました。トランス一時側と二次側のインダクタンス値をEPCOSのA_h (3950 nH/turn)を12巻き線数と３巻き線数に合わせました（569μH,84μH)
外部負荷のLTspiceシミュレーション以下
外部負荷１ΩのLTspiceシミュレーション以下
整流ダイオードのリンギング
以下約25V入力の整流ダイオード電圧共振と整流器出力の共振
以下は整流器入力(トランス↔ダイオード）の電圧波形（25V入力ケース）
LTspiceで再現してみました。以下は可能な限り同じような部品を利用してLTspice回路と波形。
以下以上と同じ条件が、整流器入力に100Ω＋1nF RC snubber配置
以下同条、100Ω並列100Ω（同化50Ω）＋1nF。
LTspiceシミュレーション以下
| Condition | Vin [V] | Iin [A] | Vout [V] | Efficiency |
|---|---|---|---|---|
| without snubber | 25.0 | 1.04 | 4.16 | 66.6 % |
| 2×100 Ω ∥ + 1 nF | 25.0 | 1.05 | 4.16 | 66.0 % |
| 100 Ω + 1 nF | 25.0 | 1.05–1.06 | 4.18 | 65.9–66.6 % |
66.6 % |
負荷別効率の整理（無負荷電力補正あり）
無負荷時でも、LDO・LED・制御回路などで入力電力が消費される。
そのため通常の効率
\eta = P_{out}/P_{in}
に加えて、無負荷入力電力を差し引いた補正後効率
\eta_{corr} = P_{out}/(P_{in}-P_{idle})
も併記した。
ここでは無負荷時の入力電力を以下とした。
- 30 V入力時:
P_{idle}=30.0\times0.05=1.50\ \mathrm{W} - 45 V入力時:
P_{idle}=45.0\times0.06=2.70\ \mathrm{W}
| Vin [V] | Iin [A] | Vout [V] | Rload [Ω] | Pin [W] | Pout [W] | η | ηcorr |
|---|---|---|---|---|---|---|---|
| 30.0 | 0.05 | 9.97 | no load | 1.50 | - | - | - |
| 45.0 | 0.06 | 14.33 | no load | 2.70 | - | - | - |
| 30.0 | 0.24 | 7.50 | 12.3 | 7.20 | 4.57 | 63.5 % | 80.2 % |
| 45.0 | 0.36 | 11.48 | 12.3 | 16.20 | 10.71 | 66.1 % | 79.4 % |
| 30.0 | 0.35 | 7.17 | 7.1 | 10.50 | 7.24 | 69.0 % | 80.5 % |
| 45.0 | 0.54 | 10.98 | 7.1 | 24.30 | 16.98 | 69.9 % | 78.6 % |
| 30.0 | 0.38 | 7.07 | 6.0 | 11.40 | 8.33 | 73.1 % | 84.2 % |
| 45.0 | 0.60 | 10.82 | 6.0 | 27.00 | 19.51 | 72.3 % | 80.3 % |
| 30.0 | 0.63 | 6.43 | 3.0 | 18.90 | 13.78 | 72.9 % | 79.2 % |
| 45.0 | 0.99 | 9.90 | 3.0 | 44.55 | 32.67 | 73.3 % | 78.1 % |
| 30.0 | 1.27 | 5.10 | 1.0 | 38.10 | 26.01 | 68.3 % | 71.1 % |
| 48.0 | 2.17 | 8.22 | 1.0 | 104.16 | 67.57 | 64.9 % | - |
無負荷電力を差し引くと、軽負荷時の見かけの効率はかなり改善する。
一方で重負荷では補正の影響は小さくなり、実際の支配要因は整流損失、銅損、循環電流などであることが分かる。
補正効率を入力電力に対してプロットすると、入力電力増加に伴い効率はやや低下する傾向が確認できる。これは主に導通損失および銅損の増加によるものである。
Closed-control & EMC measures｜ 制御フィードバックとEMI対策
出力電圧を約5Vを固定させるために、UCC3895制御ICのEAN入力にDC/DC出力V_outから20Kと6.8K分圧抵抗体を接続しました。
最初試作基板ミスの原因で、負荷入力を制御基板に長いケーブルで繋げました。
以下はDC/DC入力電圧約１２Vでの制御基板のEAN電圧（オレンジ色）と分圧抵抗体ハイサイド（水色）。
予測されていた波形はほぼ横ばい（電圧固定）です。意外とノイズが非常に多かったです。但し、当該ノイズはオシロスコープにカプリングされるdV/dtか、実際にEAN電圧にノイズが発生しているか疑いです。
オシロスコープのプローブとMOSFETやスイッチングループとの約10㎝距離があっても、ノイズカプリングの可能性があります。
DC/DC入力を約12V→約14Vに上げて、オシロスコープで表示される波形（以下）は大きく変換しました。
DC/DC入力電圧を少しだけ上げると入力電流は急激に上がり（7Ω負荷でも、0.15A → 1A以上）、トランスのmagnetosctrictionの音だけはなく、高圧ガス排出ような音（経験したことある電解コンデンサーのventing音）が基板から出て、出力電圧が不安定になります。最終的に出力電圧が落ちます。２～３回同じ挙動を再現できました。
出力電圧制御のEANセンシング線を外すと、以前と同じ、DC/DCは正常に動きます（壊れていません）。
10nFセラミックコンデンサをEANとGNDの間に配置し、挙動は前より安定化されてようです。
| Input Voltage | Output Voltage | Status / Observations |
|---|---|---|
| 12 V | 2.78 V | Stable: Normal operation. |
| 16 V | 2.50 V | Unstable: Acoustic noise present; output voltage fluctuations |
| 17 V | Failed: Output voltage drops significantly. |
以下は測定セットアップの写真、12 V 入力。
16 V入力のEAN（オレンジ）、分圧真中（水色）以下
波形に小さい瞬時的なサージと継続的、大きくない電圧変動が見えます。
分圧下側（6.8 kΩ）に 10 nF追加で挙動はわずかに改善。
| Vin [V] | Vout [V] | 挙動 |
|---|---|---|
| 16.0 | 3.62 | 安定 |
| 16.1–16.2 | ～2 | 大きく変動（回復あり） |
さらに EAN-GND直近に 10 nF + 100 nF を追加すると、Vin > 30 Vでも動作可能。ただし 16 V付近から大きな出力変動は継続。
長い配線（負荷→分圧入力）にて大きなスパイク電圧を確認。
結論：長いフィードバック配線によるノイズ重畳が支配的
フィードバック配線修正と効率評価
負荷側からの GNDセンス追加 + ツイストペア化 により出力電圧は安定化 → ✅️
以下はUCC3895のEAN電位-AGND（アナロググラウンド）電位（水色）とAGND-基板GND入力（オレンジ）。
EAN-AGND電圧（DC/DC出力電圧センシング）はかなり安定で、AGND-GND電圧波形に数mV振幅、約14MHz周波数ノイズが確認されました。
制御フィードバック動作PSFBの性能・効率評価 Performance and efficiency test of the PSFB with closed-control operation
条件: Rload = 7 Ω
| Vin [V] | Iin [A] | Pin [W] | Vout [V] | Pout [W] | η | η* | 備考 |
|---|---|---|---|---|---|---|---|
| 20.0 | 0.24 | 4.80 | 4.65 | 3.09 | 64.4% | ~70% | 静音 |
| 21.0 | 0.25 | 5.25 | 4.89 | 3.42 | 65.1% | ~71% | |
| 25.0 | 0.23 | 5.75 | 4.89 | 3.42 | 59.5% | ~66% | 磁歪音（magnetostriction） |
| 30.0 | 0.22 | 6.60 | 4.89 | 3.42 | 51.8% | ~60% | 磁歪音増加 |
| 35.0 | 0.20 | 7.00 | 4.89 | 3.42 | 48.9% | ~57% | 強い磁歪音 |
| 40.0 | 0.19 | 7.60 | 4.89 | 3.42 | 45.0% | ~54% | |
| 45.0 | 0.19 | 8.55 | 4.89 | 3.42 | 40.0% | ~50% |
条件: Rload = 1 Ω
| Vin [V] | Iin [A] | Pin [W] | Vout [V] | Pout [W] | η | η* | ノイズ |
|---|---|---|---|---|---|---|---|
| 20.0 | 0.76 | 15.20 | 3.12 | 9.76 | 64.2% | ~70% | 無音 |
| 25.0 | 0.96 | 24.00 | 4.01 | 16.08 | 67.0% | ~73% | 無音 |
| 30.0 | 1.14 | 34.20 | 4.86 | 23.62 | 69.1% | ~75% | 軽い鳴き |
| 35.0 | 1.01 | 35.35 | 4.86 | 23.62 | 66.8% | ~72% | 鳴き増加 |
| 40.0 | 0.95 | 38.00 | 4.86 | 23.62 | 62.2% | ~68% | 強い鳴き |
| η*: 無負荷消費電力を差し引いた補正効率 |
出力電圧は 約4.89 Vで安定。従来の不安定動作は、単線フィードバックとGND電位差によるノイズ重畳が主因と考えられる。
一方で、高Vinでは 磁歪（magnetostriction）による可聴ノイズ（chirping / high-pitched noise） が発生しており、これは制御ループとは別の課題である。
以下はLS MOSFET Drain～Source(PGND)の電圧波形とテストセットアップ。
Discussion